1. Field
The example embodiments relate to semiconductor memory devices, and more particularly, to a test circuit and a method for use in a semiconductor memory device, for sequentially selecting word lines from different memory blocks.
2. Description of Related Art
As the degree of integration of devices within a semiconductor memory device gradually increases, the size of circuit devices adapted within the semiconductor memory device may become relatively smaller and fabrication processes of semiconductor memory devices used for fabricating the circuit devices may become very complicated. Thus, a process margin may decrease, and may bring about an increase of failed memory cells.
When fabrication processes of a semiconductor memory device are completed, a test for the semiconductor memory devices may be performed prior to starting a sawing process as part of a packaging process. The test may be performed to check several characteristics of respective semiconductor memory devices formed on a semiconductor substrate.
Semiconductor memory devices may be tested to find failure in the fabrication process of a semiconductor substrate, the assembly process, or other processes. The failure may then be eliminated by selecting only nondefective devices.
When a fabrication failure or inconsistency between design and actual function is found out in the test result of the semiconductor memory devices, an analysis may be executed to detect the exact causes of the failure, and the throughput of semiconductor memory devices may be increased.
A test method may include providing an applied voltage of a semiconductor memory device higher than an actual use voltage, or operating the semiconductor device in a relatively high temperature. This method may be used to apply in advance a stress to the semiconductor memory device for a short time. The stress may correspond to a failure period that may be experienced in an actual use of the device, and may allow memory cells that have a higher possibility of failure to be identified before products are shipped. An electrical test like the one discussed above may be effective in increasing the reliability of products.
This test may be classified as a wafer burn-in test or a package burn-in test according to the test method.
The wafer burn-in test may be used to initially eliminate defective devices by applying a high voltage to a chip of wafer state, and the package burn-in test may be used to initially remove defectives by applying a high voltage to a chip of package state.
Conventional semiconductor memories may have undergone burn-in tests several times in a package state. The burn-in test may be used to guarantee the life and reliability of semiconductor memory devices completed in the fabrication by manufacturers.
Memory devices may be shipped for users after such test procedures. Defects from the test result may be detected mainly in a memory cell array. Causes of these defects may be as follows.
An access transistor constituting a unit memory cell of a general DRAM may be constructed of an NMOS transistor. A gate signal controlling the access transistor in an access operation, which may be high voltage, may be applied as a word line voltage. There may be a high possibility of damaging a gate oxide of the access transistor due to the stress which may result from the strong electric field which may be generated by the word line voltage having a high voltage level. Furthermore, defects may be caused in many peripheral circuits or a core part like, for example, a sense amplifier and equalizing circuit etc.
FIG. 1 illustrates a cell array structure of a general semiconductor memory device according to a conventional art.
A semiconductor memory device referred to in FIG. 1 comprises a plurality of memory banks, for example, four banks, and each memory bank may comprise plural memory blocks BLK0˜BLKn, wherein n may be a natural number greater than 1.
The memory blocks BLK0˜BLKn may be constructed of, for example, 16 or 32 blocks. Each memory block BLK0˜BLKn may comprise a plurality of word lines, for example, an m-number of WL00˜WL0m for a zeroth memory block, m being a natural number greater than 1, a plurality of bit lines, and a plurality of memory cells that may be located on intersections of the word lines WL and the bit lines BL.
FIG. 1 illustrates a plurality of memory blocks which may constitute the memory cell array. The memory blocks BLK0˜BLKn may constitute one bank of memory cells in a memory cell array or an entire memory cell array.
FIG. 2 is a table illustrating an example generation sequence of test addresses in a semiconductor memory device having a memory cell array structure shown in FIG. 1.
In the example depicted in FIG. 2, the number of memory blocks BLK is 16 and the number of word lines WL in one memory block is 512.
The test address may be constructed of 16 bits including the least significant 13bits A0˜A12. With respect to the most significant three bits of the test address, the first and second most significant bits may be an address for a bank selection, and the third most significant bit may be used to indicate when a memory bank selected by the first and second most significant bits is bisected. With respect to the least significant 13 bits, bits A9˜A12 may be block addresses to select any one of a plurality of memory blocks within a selected memory bank, and bits A0˜A8 may be a line address to select any one of plural word lines within a selected block.
Test addresses are generally generated in an address generating circuit including an address counter.
In the example depicted in FIG. 2, a memory bank etc. is already selected, thus the most significant three bits of the test address are not shown in FIG. 2.
As shown in FIG. 2, 13-bit test address RA of A0˜A12 may be generated sequentially increasing from a line address A0˜A8. That is, the address may be generated sequentially increasing from ‘0000 000000000’ to ‘0000 111111111’. Thus all of the 512 word lines WL00˜WL0511 of zeroth memory block BLK0 may be sequentially selected and enabled. If a block address A9˜A12 increases by one, a counting of line address A0˜A8 may restart. That is, test address may be generated and may be sequentially changed from ‘0001 000000000’ to ‘0001 111111111’. The test addresses RA may be generated through such method from ‘0000 000000000’ to ‘1111 111111111’.
FIG. 3 illustrates timings for a burn-in test operation according to the conventional art.
Referring to FIG. 3, an active command ACT and a test address RA may be applied in response to a first rising edge of test clock signal CLK. A zeroth word line WL00 of a zeroth memory block BLKO may be enabled in response to the test address RA. Then, a write command Write for the zeroth word line WL00 of the zeroth memory block BLKO may be applied in response to a second rising edge of the test clock signal CLK. A stress operation applied to all memory cells or at least one memory cell coupled to the zeroth word line WL00 may be performed in response to the write command Write. For the purpose of simplicity, only the least significant 3 bits of the test address RA are shown in FIG. 3.
The applied stress operation may be similar to a general write operation, except that the voltage applied through word line or bit line may be of a higher voltage having a higher level as compared with a normal operation.
When the stress operation is completed, the zeroth word line WL00 of the zeroth memory block BLK0 may be precharged in response to a precharge command PRE. Then, a next word line WL01 of the zeroth memory block BLK0 may be enabled, performing an applied stress operation. Through this operation, all 512 word lines WL0m of the zeroth memory block BLK0 may be enabled and the stress applied operation may be performed. Afterwards, a word line WL1m of the subsequent memory block BLK1 may be enabled and an applied stress operation may be performed. The applied stress operation may continue until all word lines WL of all memory blocks BLK are enabled.
In the general test method described above according to the conventional art, a test for all memory cells within one memory block may be performed, and after that, a test for another memory block may be performed. Further, two or more word lines within one memory block may not be simultaneously enabled. This may be based on a structural problem in semiconductor memory devices. This is why when operations of applying high voltage are performed at the same time, an excess current consumption may be caused.
In a conventional test method, a test may be performed for one word line for a time t1 which may be the time between the enabled time point and the precharged time point of the word line. That is, a long test time and great cost may be required. Furthermore, many semiconductor memory devices connected in parallel may have to be tested simultaneously. Thus, it may be preferable to perform all test procedures together with a sensing operation through a bit line, which may cause an overload on a burn-in test equipment.